1. Field of the invention
The present invention relates to a dynamic random-access memory (DRAM) device, and more particularly to a DRAM device that supports a partial array self-refresh operation and a method for partially refreshing a memory cell array.
2. Description of the Related Art
In portable devices or mobile devices such as mobile phones, technology is required for minimizing power consumption of batteries, so as to extend battery lifetime. As such devices have been provided with features requiring the processing of a large amount of data, such as moving picture data, DRAM chips included in such devices have been continuously increasing in capacity.
A typical DRAM device executes a periodic refresh operation, in order to preserve data stored in each cell of the device during operation. Such periodic refresh operations consume a considerable amount of battery power of a mobile device. In general, the larger the capacity of the DRAM device, the more power is consumed by the refresh operations.
To reduce the power consumed by the refresh operations, some DRAM devices adopt a partial array self-refresh (PASR) technique in which a refresh operation is executed only for that portion or subset of the entire memory that is actually in use.
FIG. 1 is a conceptual diagram illustrating a bank configuration of memory cells according to the PASR technique for a conventional single-cell DRAM. As shown in FIG. 1, according to a ½ PASR technique, a refresh operation for memory banks A and B is performed, and a refresh operation for memory banks C and D is not performed.
PASR techniques for DRAM devices are disclosed in Korean Patent No. 443909, U.S. Pat. Nos. 6,819,617, 6,590,822, Korean Patent Laid-Open Publication No. 2004-6767, and U.S. Patent Application Publication No. 2004/0100847, the contents of which are incorporated herein by reference.
Meanwhile, twin-cell memory devices have recently been introduced. By assigning two memory cells for access to a single bit of data, the twin-cell memory device requires twice as large an area as the single-cell memory device for storing the same amount of information, but provides for faster data access than the single-cell memory device due to a larger voltage variation amplitude applied to the bit lines, the amplitude being twice as large as that of the single-cell memory device.
FIG. 2 is a conceptual diagram illustrating a bank configuration of memory cells according to the PASR technique for a conventional twin-cell DRAM. When executing the PASR, the twin-cell memory device in FIG. 2 selects a pair of word lines WL0 and WL1 to refresh one bit of data.
A semiconductor memory device that can be transformed between two configuration modes; namely, a single memory cell configuration and a twin memory cell configuration, is disclosed in Korean Patent Laid-Open Publication No. 2003-89410 and U.S. Pat. No. 6,775,177, the contents of which are incorporated herein by reference.